74HC595 [Wing Shing]
8-Bit Shift Registers W ith Latched 3-State Output; 8位移位寄存器当变送器锁存三态输出
| 型号： | 74HC595 |
| 厂家： | 
WING SHING COMPUTER COMPONENTS |
| 描述： | 8-Bit Shift Registers W ith Latched 3-State Output |
| 文件： | 总8页 (文件大小：246K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-Bit Shift Registers W ith Latched 3-State Output
74HC595
GENERAL DESCRIPTION
74HC595 is fabricated with high-speed silicon
gate CMOS technology. It contains an 8-bit
serial-in, serial or parallel-out shift register and an
8-bit D-type storage register with parallel 3-state
outputs. The shift and storage register have
independent clock inputs. Both the shift register
clock (SRCK) and storage register clock (RCK)
are positive-edge triggered.
The shift register has a direct overriding clear
input (SRCL), serial data input (SER), and serial
outputs for cascading. When the output-enable
(OE) input is high, the outputs are in the
high-impedance state. If both clocks are
connected together, the shift register always is
one clock pulse ahead of the storage register.
FEATURES
• 8-bit serial-in, parallel-out shift register with storage
• Shift register has direct clear
• 8-bit D-type storage register with parallel 3-state outputs
• Two independent clocks for shift and storage register
• Wide operating power supply voltage 2-6V
• Low input current < 1µA
• Low power consumption, Max. 80µA (74HC595)
• Output driving capacity 6 mA at 5V
• Typical propagation delay 13nS
LOGIC DIAGRAM
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
2
3
15
1
4
5
6
7
13
OE
3R
C3
3S
3R
C3
3S
3R
C3
3S
3R
C3
3S
3R
C3
3S
3R
C3
3S
3R
C3
3S
3R
C3
3S
12
11
RCK
SRCK
14
2S
2R
C2
2S
2R
C2
2S
2R
C2
2S
2R
C2
2S
2R
C2
2S
2R
C2
2S
2R
C2
9
1D
C1
Q8’
SER
R
R
R
R
R
R
R
R
10
SRCL
1
WS74HC595
FUNCTIONAL DESCRIPTION
1. Truth Table
Inputs
Function
SER
X
SRCK
X
SRCL
RCK OE
X
X
L
X
X
X
X
H
L
Outputs Q1-Q8 are disabled.
X
X
Outputs Q1-Q8 are enabled.
Shift register is cleared.
X
X
X
X
↑
L
H
First stage of the shift register goes low.
Other stages store the data of previous stage, respectively.
First stage of the shift register goes high.
↑
H
X
H
X
X
X
X
Other stages store the data of previous stage, respectively.
Shift-register data is stored in the latch.
↑
X
H = High Level (steady state). L= Low Level (steady state)
X = Irrelevant (don’t care)
↑= Transition from low to high level.
2. Logic Waveform
SRCK
SER
RCK
SRCL
OE
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q8'
Note:
implies that the outputs are in 3-state mode.
2
WS74HC595
ABSOLUTE MAXIMUM RATINGS
Parameter
DC supply voltage Vcc
Value
Unit
V
- 0.5 ~ + 7.0
DC input clamp current Iik (Vi<0 or Vi>Vcc)
DC output clamp current Iok (Vo<0 or Vo>Vcc)
DC Current Drain per pin, any output (Iout)
DC supply Current, Vcc or GND (Icc)
Storage Temperature( TSTG)
20
mA
mA
mA
mA
℃
20
35
70
-65 ~ +150
Lead Temperature(TL) (Soldering, 10seconds)
260
℃
Note:
1. Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed.
RECOMMENDED OPERATING CONDITONS
Min.
2
Normal
Max.
Unit
V
Parameter
Power Supply Voltage (Vcc)
5
6
VCC=2.0V
VCC=4.5V
VCC=6.0V
VCC=2.0V
VCC=4.5V
VCC=6.0V
1.5
3.15
4.2
VIH High-level input voltage
VIL Low-level Input Voltage
V
0.5
1.35
1.8
V
VI Input Voltage
0
0
Vcc
Vcc
85
V
V
VO Output Voltage
74HC595
Operating Temperature (TA)
-40
℃
VCC=2.0V
VCC=4.5V
VCC=6.0V
Input Rise/Fall Times (tr, tf)
1000
500
ns
400
Note:
2. All unused inputs of the device must be held at Vcc or GND to ensure proper device operation.
3. If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a
potential to go into the wrong state from induced grounding, causing double clocking. Operating
with the inputs at tt = 1000 ns and Vcc = 2 V does not damage the device; however, functionally, the
CLK inputs are not ensured while in the shift, count, or toggle operating modes.
3
WS74HC595
DC ELECTRICAL CHARACTERISTICS
(Apply across temperature range unless otherwise specified)
TA = 25℃
54HC595
74HC595
MAX
MIN
Vcc
V
PARAMETER
TEST CONDITIONS
UNIT
V
MIN
TYP MAX
1.9 1.998
1.9
2
4.4 4.499
5.9 5.999
3.98 4.3
5.48 5.8
0.002
4.4
IOH = -20uA 4.5V
5.9
VOH
VI= VIH or VIL
6
V
3.84
5.34
IOH = -6 mA 4.5V
IOH = -7.8mA 6
2
V
0.1
0.1
0.1
V
0.001
0.1
0.1
IOL =20uA
4.5V
0.001
0.1
VOL
II
VI= VIH or VIL
VI = Vcc or 0
6
V
V
0.17
0.26
0.26
±100
0.33
0.33
±1000
±5
IOL = 6mA
4.5V
0.15
IOL =7.8mA
6
6
V
V
nA
uA
uA
pF
±0.1
±0.01 ±0.5
IOZ
Icc
Ci
VO = Vcc or 0, Q1-Q8
VI = Vcc or 0 IO = 0
6
6
V
V
80
8
3
10
10
2V ~ 6V
TIMING REQUREMENTS OVER RECOMMENED OPERATING FREE-AIR TEMPERATURE
RANGE (unless otherwise noted)
Parameter
Symbol Unit Guaranteed Limit
Test Condition
-40~+85
TA=25℃
6
31
36
80
5
Clock frequency
fclock MHz
Vcc=2.0V
Vcc=4.5V
Vcc=6.0V
Vcc=2.0V
25
29
SRCK or LCK high or low
SRCL low
100
Pulse duration
tw
ns
16
14
80
20
17
Vcc=4.5V
Vcc=6.0V
Vcc=2.0V
100
16
14
20
17
Vcc=4.5V
Vcc=6.0V
Vcc=2.0V
Vcc=4.5V
Vcc=6.0V
Vcc=2.0V
Vcc=4.5V
100
20
125
25
SER before SRCK↑
17
21
75
94
SRCK↑ before LCK↑
(Note 4)
15
19
Setup time
tsu
ns
13
50
10
9
16
65
13
11
60
12
11
0
Vcc=6.0V
Vcc=2.0V
Vcc=4.5V
Vcc=6.0V
Vcc=2.0V
Vcc=4.5V
Vcc=6.0V
Vcc=2~6V
SRCL low before RCK↑
50
10
9
SRCL high(inactive)
before SRCK↑
0
Hold time,
th
ns
SER after SRCK↑
Note: . 4. This setup time allows the latch to receive stable data from the shift register. The clock can
be connected together, in this case the shift register is one clock pulse ahead of the latch.
4
WS74HC595
AC ELECTRICAL CHARACTERISTICS (unless otherwise noted)
74HC595
Parameter
Parameter
Symbol From To
(Input) (Output)
Unit Vcc
Ta = 25℃
Min Typ Max
Min
5
Max
MHz 2V
4.5V
Maximum
clock
fmax
6
26
38
42
50
17
14
50
17
25
29
CL=50pF
CL=50pF
31
36
6V
frequency
2V
200
40
160
32
ns
4.5V
6V
SRCK Q8'
27
34
2V
150
30
187
37
Maximum
Propagation
Delay
tpd
4.5V
6V
LCK
LCK
Q1-Q8
ns
ns
ns
32
14
60
22
26
200
40
2V
250
50
(Clock to Q)
4.5V
6V
CL=150pF
CL=50pF
Q1-Q8
43
19
51
18
34
175
35
Maximum
Propagation
Delay (SRCL
to Q8'
2V
219
44
tPHL
4.5V
6V
SRCL QH'
37
15
30
2V
187
37
40 150
4.5V
6V
CL=50pF
CL=150pF
CL=50pF
15
13
30
26
Maximum
Propagation
Delay
32
2V
250
50
OE Q1-Q8
ns
70 200
ten
4.5V
6V
23
19
42
40
34
(OE to Q)
43
2V
250
50
200
4.5V
6V
tdis
OE Q1-Q8
Q1-Q8
ns
23 40
20 34
43
2V
75
28
8
60
12
10
75
15
13
4.5V
6V
15
13
Maximum
Output
6
2V
95
CL=50pF
28
8
4.5V
6V
19
Rising and
Falling Time
tt
Q8'
ns
16
6
2V
265
53
45 210
17 42
13 36
4.5V
6V
CL=150pF
Q1-Q8
45
Power
Dissipation
Capacitance
CPD
pF
400
–
–
PARAMETER MEASUREMENT INFORMATION
Vcc
PARAMETER
RL
CL
S1
S2
t
PZH
PZL
PHZ
PLZ
S1
S2
1 kΩ
Open
Closed
Open
Closed
Closed
Open
Closed
Open
50 pF or
150 pF
Test
Point
RL
ten
t
From
Output
Under Test
t
1kΩ
50 pF
CL
tdis
t
50 pF or
150 pF
tpd or tt
-
Open
Open
5
WS74HC595
AC SWITCHING WAVEFORM AND AC TEST CIRCUIT
Voltage Waveforms 1. Propagation Delay and Output Transition Times
Vcc
Input
50%
tPLH
50%
50%
tPHL
0 V
V
OH
In-Phase
Output
90%
tr
90%
50%
10%
10%
VOL
tf
tPHL
90%
tPLH
50%
10%
V
OH
90%
50%
Out-of-Phase
Output
10%
VOL
Voltage waveforms 2. Enable And Disable Times For 3-State Outputs
Output
Control
(Low-Level
Enabling)
Vcc
50%
tPZL
50%
0 V
tPLZ
10%
Output
≈Vcc
50%
≈Vcc
Waveform1
VOL
VOH
tPZH
Output
Waveform
2
90%
50%
≈0 V
tPHZ
Voltage waveforms 3. Setup And Hold and Input Rise And Fall Times
Vcc
Reference
Input
50%
0 V
th
tsu
Vcc
0 V
Data
Input
90%
90%
50%
10%
50%
10%
tr
tf
6
WS74HC595
Voltage waveforms 4. Pulse Durations
High-Level
Vcc
0V
Vcc
0V
50%
Pulse
50%
tw
50%
50%
Low-Level
Pulse
Note:
5. CL includes probe and test-fixture capacitance.
6. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by
generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
7. For clock inputs, fmax is measured when the input duty cycle is 50%.
8. The outputs are measured one at a time, with one input transition per measurement.
9. tPLZ and tPHZ are the same as tdis.
10. tPZL and tPZH are the same as ten.
11. tPLH and tPHL are the same as tpd.
PIN DESCRIPTION
PIN NO.
SYMBOL
DESCRIPTION
Parallel data outputs
15, 1, 2, 3, 4, 5, 6, 7
Q1 – Q8
Q8’
9
Serial data output
10
SRCL
Shift register reset input (active low)
Shift and storage register clock inputs
(triggered at positive edge)
Output enable input (active low)
Serial data input
11, 12
SRCK, RCK
13
14
8
OE
SER
GND
VCC
Ground (0V)
16
Positive power supply
11
SRCK
12
RCK
Vcc
Q2
Q3
Q
16
1
9
Q
8’
Q
1
15
1
Q
1
Q2
Q3
SER
OE
4
2
14
Q
5
Q
6
3
SER
Q
4
4
Q
Q
RCK
5
5
6
6
Q7
SRCK
SRCL
Q7
Q8
7
Q8
SRCL OE
10 13
9
8
GND
Q
8’
Pin Configuration
Logic Symbol
7
WS74HC595
PAD DIAGRAM
The Coordinate of Each Pad
SRCK
SRCL
RCK
Q8’
Q8
GND
OE (-615.1, -748.2)
SER (-398.1, -748.2)
Q1 (-243.3, -762.4)
VCC (118.3, -789.2)
Q2 (479.8, -714.6)
Q3 (479.8, -520.6)
Q4 (479.8, -264.8)
Q5 (479.8, -70.2)
Q6 (479.8, 185.0)
Q7 (479.8, 379.6)
Q8 (479.8, 635.4)
GND (105.8, 683.3)
Q8’ (-199.4, 683.3)
SRCL (-359.7, 673.2)
SRCK (-581.0, 689.2)
RCK (-600.9, 534.4)
Q7
Q6
74HC595
Die Size = 57 mil X 74 mil
Pad Size = 90 um X 90 um
Q5
Q4
Q3
Q2
Note: Substrate should be connected to Vcc or
OE
SER
Q1
left it open.
VCC
8
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